Long time delay line



March 23, 1965 F. R. FLUHR ETAL 3,175,195

LONG TIME DELAY LINE Filed Oct. 31, 1961 70 E TP 152.3 SCANNER 1 "1 HIGHIMPEDANCE SCANNING CATHODE FOLLOWERS PULSE GENERATOR INPUT 403 1 Fun-"1.OUTPUT o---|NSERTION DRIVER-p DELAY STORAGE i PROGRAMMER E l E -32 r5232" w l4 l3 L 25 INSERTION n DRIVER 21 21' 27 B l5 24 *"71 I2 9/ 1e IB'l I8 26 i CF :7 v17 |7n 19 l9' |9 r I Q FILTER L... ...J I! I n 30 I b3l0 M22 22 w-zz OUTPUT E1515 (1 n H l b 1 F1 g Lu I I g 7' l Q i i 1 i l C:3 I i l I I g H n: d i m I l I I E 2 l I l I l I l e E u a I l i I l ll I l l To T| T2T3T4T5 T| M E T6T7T8 INVENTORj FREDERICK R. FLUHR DONALDJ. MCLAUGHLIN ATTORNEY United States Patent Ofitice 3,175,195 PatentedMar. 23, 1965 3,175,195 LONG TIME DELAY LiNE Frederick R. Fluhr, OxonHill, Md, Donald 5. McLaughlin, Washington, D.C., and Schuyler C.Wardrip, Springfield, Va., assignors to the United States of America asrepresented by the Secretary of the Navy Filed Get. 31, 1961, Ser. No.149,135

4 Claims. (Cl. 340-473) (Granted under Title 35, US. Code (1952), see.266) The invention described herein may be manufactured and used by orfor the Government of the United States of America for governmentalpurposes without the payment of any royalities thereon or therefor.

This invention relates to improvements in time delay circuits for dataprocessing systems and more particularly to an improved circuit andmethod for obtaining relatively long, controlled time delays.

A delay line is a device which will accept a time-varying electricalsignal at its input, and within certain limits of amplitude, time rateof change, and accuracy, deliver this signal to its output terminalfollowing some predictable delay. Numerous techniques to accomplish thiseffect, such as lumped or distributed constant lines, ultrasonic wavesin solids or liquids and electromechanical or electromagnetic recordinghaving been developed in the prior art, but the field is limited by lackof a simple, reliable delay line which will provide time delays up toseveral seconds in length and still be capable of a fast actingcontinuous but variable readout.

Delay lines employing lumped or distributed electrical constants exhibita fixed delay for a given configuration, and experience a progressivedeterioration of the signal amplitude with increasing delay time. Eithertype of line is limited in that precautions must be taken to avoidupsetting impedances, the signals change at every point along the linefrom input to output at a constant rate and the delays range frommillimicrosecouds to milliseconds.

Prior delay lines have also converted signals to a sound wave oremployed the signal to modulate an ultrasonic carrier which istransmitted acoustically through a solid, liquid or gas having thedesired transit time delay. Transducers are usually employed to sampleor tap the signal energy at variable positions along the carrier butthen the system is limited by certain minimum distances that arenecessitated due to the physical size of the carrier and transducers.Delay media which have been employed in systems previously reduced topractice have included air, Water, mercury, metal Wires or rods (usuallyof magnetostrictive material) and quartz plates. Delay times, however,must remain fixed for a given configuration and practical time delaysrange from a few microseconds to several milliseconds in devices ofreasonable size.

Electromechanical and electromagetic recording techniques have also beenemployed as a delay line but to avoid endless consumption of recordingmedia, a closed loop system providing for erasure and re-use of themedia must be employed. While time delays are theoretically withoutlimit for extended operations, the media itself is subject to wear andneeds replacement. Further limiting their application is the need fordriving mechanisms necessary to produce relative mechanical movements.

The most closely related previously existing delay line, is described inthe British periodical Nature, January 25, 1952, pages 148 to 14-9 by I.M. Ianssen wherein an amplifier is used to isolate the respectivecapacitors. The delay line, however, is limited in that the transferoperation must be carried out at twice the transfer cycle rate,amplifier distortion or noise may introduce undesirable discrepancies inthe transfer process and the equipment requirements are large since twoamplifiers, capacitors and relay contacts are required for each elementof time resolution in the stored signal.

Accordingly, it is an object of our invention to provide an improvedmethod and device for storing electrical in formation for relativelylong periods of time without undue complexity.

It is another object of our invention to provide an improved storagedevice for retaining data over long periods of time and to provide meansfor rapid, continuous and variable readout.

It is a further object of this invention to provide a signal processingcircuit capable of causing a time delay of several seconds and capableof passing frequencies limited only by the sampling rate used to causethe time delay.

it is still a further object of our invention to provide a storagedevice useful as a signal detector wherein each Stored element of aninput signal is made available simultaneously and with a minimum ofoperations for rapid sampling operations.

Yet another object of this invention is to provide a long time delayline capable of being employed as a stor' age device for patternrecognition of a signal by repetitively scanning each element of timeresolution.

Still another object of our invention is to provide a storage devicewhereby the delay line permits a wide continuous but variable range ofsubstantially instantaneous control over the total delay.

According to the invention, a data signal is supplied to a delay linerequiring only one capacitor and one relay contact for each storedelement of time resolution in the stored signal. The circuit requiresonly one read-in amplifier and one readout amplifier while performingonly one readin-readout operation for each time element, or 11operations between a signal element entering the line and the time it isdelivered to the output, Where n is the number of capacitors in thedelay line. Each signal element is also made simultaneously available byn cathode followers whereby rapid sampling operations may be performedand unlimited scanning readout of each stored element is provided.

The exact nature of this invention together with other objects, novelfeatures and advantages thereof, will be readily apparent fromconsideration of the following description relating to the annexeddrawing wherein similar reference numerals refer to similar parts andwherein:

FIGURE 1 shows a schematic diagram, partially in block form, of thedelay line in accordance with the principles of our invention;

FIGURE 2 is an illustration of the waveforms encountered for properoperation of the delay line shown in FIGURE 1; and

FIGURE 3 is a block diagram showing a signal scanning system employingthe delay line of our invention.

Referring now to the drawings and in particular to FIG. 1, the delayline of this invention is shown as comprising an insertion driverlll forimpressing data in the form of a pulsed input signal on the line and areadin relay arm ll actuated by a readin relay coil 12. Arm

3 11 is also arranged so as to be able to connect a common line 13through input contact point 14 which with contact 15, forms a threeterminal readin relay switch. Also connected along common line 13 are nnumber of leads 16, 16 16, the number depending upon, the signalbandwidth and delay desired. The stored input signal is divided intoseparate elements of time resolution representative of data information,with each element stored by a separate capacitor 17, 17' 17. Eachcapacitor is connected to common line 13 by means of a storage relay arm18, 18' 18 which is actuated by a storage relay coil 19, 19' 19 and withcontacts 26, 20' 2t) and 21, 21' 21 forms a two way relay switch. Therespective storage relays are controlled from input terminals 22, 22' 22wherever a programmed signal is applied. Common line 13 is also providedwith a readout contact point 23 which with contact 24, relay arm 25 andrelay coil 26 form a two way readout relay switch whereby the commonline 13 can be connected to output ircuit 27.

Circuit 27 comprises a series connected high impedance cathode follower28 and filter 29. The readin switch relay is actuated by a controlsignal being applied to terminal 30 while the readout switch relay isactuated by applying a control signal to terminal 31.

Each capacitor is also provided with an output contact, 32, 32' 32 so asto make each stored signal element simultaneously available for furtherprocessing such as shown in FIG. 3.

The operation of the circuit is best seen by considering the pulsewaveforms shown in FIG. 2. Neglecting switching time delays and assumingthat the relays operate from positive signals, the waveforms shown inFIG. 2v will cause proper operation of the delay line shown in FIG. 1.As shown in FIG. 1, at time zero (T all the switches are in their rest(or open) position. Starting at time T storage relay coil 19 isenergized by a signal (FIG. 2a) impressed on program input terminal 22causing capacitor 17 to be connected to the common line 13.Simultaneously at time T readout relay coil 26 is energized (FIG. 2d)for approximately one-half /2) the time that coil 19 is energized. Thiscauses the voltage or signal element stored in capacitor 17 to beconnected to the output circuit, allowing the voltage or signal elementon capacitor 17 to be read out through a sample and hold cathodefollower 28.. At T approximately half /2) way through the time cyclethat storage coil 19 is energized, readout coil 26 is tie-energized anda pulse applied to program terminal 36 (FIG. 2e) energizing readin relaycoil 12. This allows capacitor 17 to be connected to signal source 111and causes capacitor 17 to be charged to the signal voltage at thatinstant representative of the signal from the driver 1d. Readin coil 12is then de-energizcd followed by the storage relay switch coil 19.Storage relay coil 19' is then energized (FIG. 2b) at time T and againsimultaneously, readout relay coil is energized by applying a controlpulse to program terminal 31, capacitor 17 being connected to the outputsample and hold cathode follower 28. At time T approximately half waythrough the pulse cycle applied to terminal 22', readout coil 26 isde-energized and momentarily at T readin coil 12 is again energizedallowing capacitor 17 to be charged to the voltage value present atinput contact point 1%. This operation is repeated for n capacitors andrelays (time T to T and when the program has passed through :1 steps,the signal returns to terminal 22 and begins to repeat the operation.Thus the output signal is n switching periods behind the input signaland is designated in FIG. 2 as the time delay between T and T It shouldbe appreciated that the present invention is not to be limited to anyparticular set of values for the circuit components or means foraccomplishing the switching operation and the programming signals may bedeveloped by any type of counting device which will provide the propertime and waveforms.

It should also be appreciated that our invention only requires onecapacitor and one relay contact for each stored element of timeresolution in the stored signal. It should also become apparent thatthis circuit will perform only one readin-readout operation for eachtime element and that n operations will be performed between a signalelement entering the line and the time it is delivered to an outputcircuit causing the delay, where n is the number of signal elementsstored.

By connecting a high impedance cathode follower to each of thecapacitors at terminals 32, 32' 32 a unique signal scanning systembecomes possible. Considering in particular FIG. 3, n number of cathodefollower circuits 60 are coupled to 11 number of storage elements in adelay storage 411 which is the delay line shown in PEG. 1. This allowsfor means for providing simultaneously for readout, each element of timeresolution of the stored input signal. If each of the outputs of thecathode foliowers are then scanned at a high rate such as by scanner 7%an output signal representative of a func-- tion of the respectivecathode followers is provided at output terminal 31). The scanner issynchronized with the programmer 50 through pulse generator 91) therebyproviding a further unique signal detecting and processing system.

By varying the scan pattern and/ or the programming, a wide continuousrange of instantaneous control over the elements of time resolutionstored in delay unit 49 becomes possible.

A unique feature of our invention is that the delay of the input signalfrom driver 10 is only limited by the sampling rate from programmer 51?.

This invention has been utilized in providing up to steps in the delayline with a signal decay of less than 1% of the input value of eachstored element while making every element of a stored signalsimultaneously available for rapid sampling operations with a minimum ofoperations.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood, that within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described.

What is claimed is:

1. In a storage device for retaining data over long periods of time, thecombination of, a common transmission line, a readin switch, means forconnecting and disconnecting said switch to said line, a data signalsource coupled to said readin switch, a readout switch, means forconnecting and disconnecting said readout switch to said line, 21 numberof terminals between said readin switch and said readout switchconnected to said common line, 11- number of means for storing nelements of said data signal, switch means for connecting anddisconnecting the terminals of said common line to n number of storingmeans and programming means for sequentially controlling the operationof all of said switches and switch means and for varying the rate atwhich all of said switches and switch means operate.

2. In the storage device as set forth in claim 1, wherein means are alsoprovided for repetitively scanning the n number of storing means.

3. In a long time delay circuit, the combination of, a data signalsource comprising n number of bits, a common transmitting line, readinswitch means for connecting and disconnecting said data signal source tosaid line, first output utilizing means, readout switch means forconnecting and disconnecting said first output utilizing means to saidline, it number of terminals distributed between said readin switch andsaid readout switch on said transmitting line, it number of storagemeans, n storage switch means for connecting and disconnecting said Itnumber of storage means to said it number of terminals, means forindividually and in ordered sequence actuating each of said storageswitch means to connect respective storage means and line terminals fora predetermined time period, means for actuating said readout switchmeans for one-half the time period each of said storage switch means areactuated, means for actuating said readin switch means for a portion ofthe remaining time period each of said storage means are connected tosaid line terminals and after said readout switch means are disconnectedfrom said line, second output utilizing means for making It number ofstorage means instantaneously available and sampling means for scanningsaid second output utilizing means.

4. In the long time delay circuit as set forth in claim 3 ReferencesCited by the Examiner UNITED STATES PATENTS 2,449,819 9/48 Purington333-29 2,833,936 5/58 Ress 340-173 2,842,756 7/58 Johnson 333-293,132,325 5/64 Bray 340-173 IRVING L. SRAGOW, Primary Examiner.

3. IN A LONG TIME DELAY CIRCUIT, THE COMBINATION OF, A DATA SIGNALSOURCE COMPRISING N NUMBER OF BITS, A COMMON TRANSMITTING LINE, READINSWITCH MEANS FOR CONNECTING AND DISCONNECTING SAID DATA SIGNAL SOURCE TOSAID LINE, FIRST OUTPUT UTILIZING MEANS, READOUT SWITCH MEANS FORCONNECTING AND DISCONNECTING SAID FIRST OUTPUT UTILIZING MEANS TO SAIDLINE, N NUMBER OF TERMINALS DISTRIBUTED BETWEEN SAID READING SWITCH ANDSAID READOUT SWITCH ON SAID TRANSMITTING LINE, N NUMBER OF STORAGEMEANS, N STORAGE SWITCH MEANS FOR CONNECTING AND DISCONNECTING SAID NNUMBER OF STORAGE MEANS TO SAID N NUMBER OF TERMINALS, MEANS FORINDIVIDUALLY AND IN ORDER SEQUENCE ACTUATING EACH OF SAID STORAGE SWITCHMEANS TO CONNECT RESPECTIVE STORAGE MEANS AND LINE TERMINALS FOR APREDETERMINED TIME PERIOD, MEANS FOR ACTUATING SAID READOUT SWITCH MEANSFOR ONE-HALF THE TIMED PERIOD EACH OF SAID STORAGE SWITCH MEANS AREACTUATED, MEANS FOR ACTUATING AND READIN SWITCH MEANS FOR A PORTION OFTHE REMAINING TIME PERIOD EACH OF SAID STORAGE MEANS ARE CONNECTED TOSAID LINE TERMINALS AND AFTER SAID READOUT SWITCH MEANS ARE DISCONNECTEDFROM SAID LINE, SECOND OUTPUT UTILIZING MEANS FOR MARKING N NUMBER OFSTORAGE MEANS INTANTANEOUSLY AVAILABLE AND SAMPLING MEANS FOR SCANNINGSAID SECOND OUTPUT UTILIZING MEANS